畢業(yè)設(shè)計論文 外文文獻翻譯 單片機類 AT89C2051 中英文對照

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1、AT89C2051 Author:Yuan Zhenming,Zhang Liang,Zhan Guohua; From: http://www.webCT.com AT89C2051 is made in the ATMEL Corporation, which is the low-voltage, high-performance CMOS8-bit microcontroller, Tablets containing repeated 2k bytes of program memory erasable read-only (PEROM) and random 128byt

2、es data memory (RAM), device using ATMELs high density, non-volatile memory technology, Compatible with the standard of MCS-51 instruction set, built-chip 8-bit general-purpose central processing unit and repeatedly write the Flash memory, which can effectively reduce the development costs. AT89C205

3、1 features a powerful single-chip can provide cost-effective in many Applications. Main features: Compatible the MCS51 command system; Contains the 2KB memory re-programming FLASH (1000); 2.7 ~ 6V voltage range; the whole Static work: 0Hz ~ 24KHz; Secrets 2 Program Memory Lock 128 8-bit int

4、ernal RAM 15 programmable I / O lines Two 16-bit timer / counter 6 interrupt sources, two external interrupt sources Programmable Serial Channel High Precision Voltage Comparator （P1.0，P1.1，P3.6）； Have the output port of the LED direct drive Low-power idle and power-down mode The pin Pictu

5、re of AT89C2051 Picture one the pin of AT89C2051 AT89C2051’s functional description: VCC: Power Supply Voltage GND: land P1 port: P1 mouth is a group of 8-bit bi-directional I / O interface, P1.2 ~ P1.7 provide internal pull-up resistor,P1.0 and P1.1 internal s

6、upreme pull-up resistor. P1 mouth output buffer can absorb the current 20mA and direct-drive LED.When Programming and calibration, P1 mouth as the eighth address receive. P3 mouth: P3 port P3.0 ~ P3.5, P3.7 is the internal pull-up resistor with the seven bi-directional I / O interface. Did not brin

7、g out the P3.6，It as a generic I / O port, but can not visit. Can be used as a fixed-chip input comparator output signal. when P3 write 1, they were highed the internal pull-up resistor can be raised as an input port. P3 port special function as shown in table 1: Table 1 P3 mouth’s special feat

8、ures 引腳 功能特性 P3.0 RXD （串行輸入口) P3.1 TXD （串行輸出口） P3.2 (外中斷0) P3.3 (外中斷1) P3.4 T0 (定時/計數(shù)器0外部輸入) P3.5 T1 （定時/計數(shù)器1外部輸入） RST：Reset output. When the oscillator device reset, RST pin to maintain the high level of two machine cycle time. XTAL1: the RP-oscillator amplifier and internal cloc

9、k generator input. Timer Overview of the Timer 89C2051 single-chip-chip has two 16-bit timer / counter, That is the timer 0 (T0) and Timer 1 (T1). They all have from time to time and event count function, Can be used for timing control, delay of external events, such as counting and testing occa

10、sions. Timer’s T0 and T1—— two 16-bit timers in fact is 16-bit counter plus 1. Among them, T0 compositioned by the two 8-bit special function registers TH0 and TL0; T1 posed by the TH1 and TL1. These functions were controled by the special function registers TMOD and TCON When set to the work in

11、the timing, Through the pin count of the external pulse signal. When the input pulse signal generated by the falling edge of 1-0, The value of timer plus 1. At of every machine cycle during the S5P2 sampling pin T0 and T1 the input level, if a machine cycle before sample value of 1, The next machine

12、 cycle sampling value is 0, The counter plus 1. Since then during S3P1 of the machine cycle, New value will into the counter.so Detection of a 1-0 transition of the two machine cycles,So The maximum count frequency of oscillation frequency of 1 / 24. In addition to the option of work from time to ti

13、me or count, Each timer / counter have four kinds of work mode, That is, each of timer circuit kinds of four constitute a structural model Two low-power mode Idle mode In idle mode, CPU to maintain sleep and all-chip peripherals remain active, this way generated in Software, At this point, Chip

14、RAM and all the contents of special function registers remain unchanged. Idle mode was terminated by any interrupt request permission to or hardware reset. P1.0 and P1.1 ,in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."

15、It should be noted that: when uses of hardware reset Termination idle mode, AT89C2051 is usually stopped from the program until the internal reset control of the two machine cycles before the restore procedure Service. In this case the hardware within the prohibition of the reading and writing of i

16、nternal RAM, However, to allow access to ports, To eliminate the Hardware reset in the idle mode of port accidents may write, In principle, to enter the idle mode of instruction should not be under the command of a pin or an external memory port for a visit. Power-down mode In power-down mode, the

17、 oscillator to stop working, enter the power-down mode ,Instructions, who was the last one, the implementation of the Directive, Chip RAM and all the contents of special function registers the termination of the previous power-down mode be frozen. To withdraw from power-down mode is the only way to

18、reset the hardware, Reset will redefine all the Special Function Registers but Does not change the contents of RAM before the the Vcc work returned to normal levels Shall be null and void and must be reset to maintain a certain period of time in order to restart and oscillator stability P1.0 and P1

19、.1 in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1." Oscillator Oscillator connected client XTAL1: RP-oscillator amplifier and internal clock generator input XTAL2: RP-oscillator amplifier output Characteristics of Osc

20、illator XTAL1, XTAL2 ware the RP-chip oscillator amplifier inputs and outputs, Quartz crystal can be composed of the clock oscillator or ceramic oscillator, For more information from the external input clock driver AT89C2051, XTAL1 input clock signal from, XTAL2 should be left vacant.As the input

21、to the internal circuit is a 2-flip-flop, Therefore, the external clock signal input without special requirements, However, it must comply with the maximum level and minimum norms and timing AT89C2051 作者：Yuan Zhenming, Zhang Liang, Zhan Guohua； 來自：http://www.webCT.com AT89C2051

22、是美國ATMEL公司生產(chǎn)的低電壓、高性能CMOS8位單片機，片內(nèi)含2k bytes的可反復擦寫的只讀程序存儲器（PEROM）和128bytes的隨機數(shù)據(jù)存儲器（RAM），器件采用ATMEL公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標準MCS-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器和可反復擦寫的Flash存儲器，可有效地降低開發(fā)成本。功能強大AT89C2051單片機可提供許多高性價比的應用場合。 3.2主要功能特性： *兼容MCS51指令系統(tǒng)； *2KB可重編程FLASH存儲器（1000次）； *2.7～6V電壓范圍； *全靜態(tài)工作：0Hz～24KHz； *2級程序存儲器保密鎖定；

23、 * 1288位內(nèi)部RAM； *15條可編程I/O線； *兩個16位定時器/計數(shù)器； *6個中斷源，兩個外部中斷源； *可編程串行通道； *高精度電壓比較器（P1.0，P1.1，P3.6）； *直接驅(qū)動LED的輸出端口； *低功耗空閑和掉電模式 AT89C2051的管腳引腳圖如圖2所示。 圖1 AT89C2051封裝管腳引腳圖 AT89C2051引腳功能說明： VCC：電源電壓 GND：地 P1口：P1口是一組8位雙向I/O接口，P1.2～P1.7提供內(nèi)

24、部上拉電阻，P1.0和P1.1內(nèi)部無上拉電阻。P1口輸出緩沖器可吸收20mA的電流并可直接驅(qū)動LED。編程和校驗時， P1口作為第八位地址接收。 P3口：P3口的P3.0～P3.5、P3.7是帶有內(nèi)部上拉電阻的7個雙向I/O接口。P3.6沒有引出，它作為一個通用的I/O口，但是不可訪問?？勺鳛楣潭ㄝ斎氲钠瑑?nèi)比較器的輸出信號。當P3口寫入1時，它們被內(nèi)部的上拉電阻拉高并可作為輸入端口。P3口的特殊功能如表1所示： RST：復位輸出。當振蕩器復位器件時，要保持RST腳兩個機器周期的高電平時間。 XTAL1：振蕩器的反相放大器及內(nèi)部時鐘發(fā)生器的輸入端。 XTAL2：振蕩器反相放大器的輸出端。

25、 表1 P3口的特殊功能 引腳 功能特性 P3.0 RXD （串行輸入口) P3.1 TXD （串行輸出口） P3.2 (外中斷0) P3.3 (外中斷1) P3.4 T0 (定時/計數(shù)器0外部輸入) P3.5 T1 （定時/計數(shù)器1外部輸入） 定時器 定時器概述 89C2051單片機片內(nèi)有兩個16位定時器/計數(shù)器，即定時器0（T0）和定時器1（T1）。它們都有定時和事件計數(shù)功能，可用于定時控制、延時、對外部事件計數(shù)和檢測等場合。 定時器T0和T1兩個16位定時器實際上都是16位加1計數(shù)器。其中，T0由兩個8位特殊功能寄存

26、器TH0和TL0構(gòu)成；T1由TH1和TL1構(gòu)成。這些功能都由特殊功能寄存器TMOD和TCON所控制。 設(shè)置為定時工作方式時，定時器計數(shù)AT89C2051片內(nèi)振蕩器輸出的經(jīng)12分頻后的脈沖，即每個機器周期使定時器的數(shù)值加1直至計滿溢出。當AT89C205采用12MHz晶振時，一個機器周期為1s,計數(shù)頻率為1MHz。 設(shè)置為計數(shù)工作方式時，通過引腳對外部脈沖信號計數(shù)。當輸入脈沖信號產(chǎn)生由1至0的下降沿時，定時器的值加1。在每個機器周期的S5P2期間采樣T0和T1引腳的輸入電平，若前一個機器周期采樣值為1，下一個機器周期采樣值為0，則計數(shù)器加1。此后的機器周期S3P1期間，新的數(shù)值裝入計數(shù)器

27、。所以，檢測一個1至0的跳變需要兩個機器周期，故最高計數(shù)頻率為振蕩頻率的1/24。除了可以選擇定時或計數(shù)工作方式外，每個定時器/計數(shù)器還有4種工作模式，也就是每個定時器可構(gòu)成4種電路結(jié)構(gòu)模式。 兩種低功耗模式 空閑模式 在空閑模式下，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式有軟件產(chǎn)生。此時，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請求或者硬件復位終止。 P1.0和P1.1在不使用外部上拉電阻的情況下應設(shè)置為“0”，或者在使用上拉電阻的情況下設(shè)置為“1”。 應注意的是：在用硬件復位終止空閑模式時， AT89C2051通常從

28、程序停止一直到內(nèi)部復位獲得控制之前的兩個機器周期處回復程序執(zhí)行。在這種情況下片內(nèi)硬件禁止對內(nèi)部RAM的讀寫，但允許對端口的訪問，要消除硬件復位終止空閑模式對端口意外寫入的可能，原則上進入空閑模式指令的下一條指令不應對端口引腳或外部存儲器進行訪問。 掉電模式 在掉電模式下，振蕩器停止工作，進入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復位，復位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容在Vcc恢復到正常工作電平前，復位應無效且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。P1.0和P1.1在不使用外部上拉電阻的情況下應設(shè)置為“0”，或者在使用上拉電阻的情況下設(shè)置為“1”。 振蕩器----振蕩器連接端 XTAL1:振蕩器反相放大器以及內(nèi)部時鐘發(fā)生器的輸入端 XTAL2:振蕩器反相放大器的輸出端 振蕩器特征 XTAL1、XTAL2為片內(nèi)振蕩器的反相放大器的輸入和輸出端，如圖3所示?？刹捎檬⒕w或者陶瓷振蕩器組成時鐘振蕩器，如需從外部輸入時鐘驅(qū)動AT89C2051,時鐘信號從XTAL1輸入，XTAL2應懸空。由于輸入到內(nèi)部電路是經(jīng)過一個2分頻觸發(fā)器，所以輸入的外部時鐘信號無需特殊要求，但它必須符合電平的最大和最小值及時序規(guī)范。