錫林右軸承座組件工藝及夾具設計【鉆φ13孔】【說明書+CAD】

錫林右軸承座組件工藝及夾具設計【鉆φ13孔】【說明書+CAD】,鉆φ13孔,說明書+CAD,錫林右軸承座組件工藝及夾具設計【鉆φ13孔】【說明書+CAD】,錫林,軸承,組件,工藝,夾具,設計,13,說明書,CAD 大連水產(chǎn)學院本科畢業(yè)論文(設計) 外文翻譯 單片集成MEMS技術(shù) 在過去的20年中，CMOS技術(shù)已成為集成電路主要制造工藝，制造成本下降的同時，成品率和產(chǎn)量也得到很大提高，COMS工藝將繼續(xù)以增加集成度和減小特制尺寸向前發(fā)展。當今，CMOS集成工藝不僅被利用在集成電路設計上，而且，也被利用在很多微傳感器和微執(zhí)行器上，這樣可以把微傳感器與集成電路集成在一起，構(gòu)成功能強大的智能傳感器。隨著微傳感應用范圍的不斷擴大，對傳感器的要求也越來越高，對未來微傳感器的主要要求是：微型化和集成化；低功耗和低成本；高精度和長壽命；多功能和智能化。硅微機械和集成電路的一體化集成，可以滿足上述要求。目前，集成傳感器的產(chǎn)品多數(shù)采用混合集成，單片集成的比例很小。而實現(xiàn)單片集成是實現(xiàn)傳感器智能化的關(guān)鍵，特別是單片集成MEMS傳感器技術(shù)也是當今片上系統(tǒng)芯片能否實現(xiàn)的關(guān)鍵技術(shù)之一。可見，對各種單片集成MEMS技術(shù)難點進行分析以及給出目前已有的各種單片集成MEMS技術(shù)是非常必要的。 1.單片集成MEMS技術(shù)的優(yōu)勢和面臨的挑戰(zhàn) 實現(xiàn)MEMS和CMOS共同工作是分別制造MEMS傳感器和CMOS集成電路，然后，從各自的晶片切開，固定在一個共同的襯底上，并且，連線鍵合，這樣就實現(xiàn)兩者的集成，這就是所謂的混合（hybrid）方法。這種方法不會產(chǎn)生MEMS制造過程對CMOS電路的污染，同時，兩者生產(chǎn)過程互不干擾。但是，由于信號經(jīng)過鍵合點和引線，導致在高頻應用時，信號傳輸質(zhì)量下降，并且，開發(fā)兩套生產(chǎn)線增加了產(chǎn)品的成本。為了解決一些性能問題，并降低制造成本，提出把MEMS部分做在和CMOS電路同一塊襯底上，也就是產(chǎn)生了與CMOS工藝兼容單片集成MEMS技術(shù)或叫CMOS-MEMS技術(shù)。這種方法相對混合方法總的來說有如下優(yōu)勢：第一，性能能得到很大的提高，因為寄生電容和串擾現(xiàn)象可以顯著減?。坏诙?，混合方法需要復雜的封裝技術(shù)以減小傳感器接口的影響，而單片集成方法需要的封裝技術(shù)相對簡單，所以，降低傳感器成本；第三，單片集成傳感器技術(shù)也是陣列傳感器的需要，是克服陣列傳感器與外圍譯碼電路互連瓶頸的一種有效方法；第四，開發(fā)單片集成MEMS產(chǎn)品比開發(fā)混合MEMS產(chǎn)品所需的時間短，而且，開發(fā)成本低。 單片集成MEMS技術(shù)根據(jù)MEMS器件部分與CMOS電路部分加工順序不同可以分為前CMOS（pre-CMOS）、混合CMOS（intermediate-CMOS）及后CMOS（post-CMOS）集成方法。 post-CMOS方法是在加工完CMOS電路的硅片上，通過一些附加MEMS微細加工技術(shù)以實現(xiàn)單片集成MEMS系統(tǒng)，目前，單片集成MEMS技術(shù)主要以這種方法為主。post-CMOS方法主要問題是MEMS加工工藝溫度會對前面的CMOS電路性能產(chǎn)生影響，更為嚴重的是后面高溫MEMS加工工藝溫度與前面CMOS工藝金屬化不兼容。以目前研究最多的多晶硅作為結(jié)構(gòu)層的MEMS為例，使磷硅玻璃致密化退火溫度為950℃，而使作為結(jié)構(gòu)層多晶硅的應力退火溫度則達到1050℃，這將使CMOS器件結(jié)深發(fā)生遷移。特別是800℃時淺結(jié)器件的結(jié)深遷移就會影響器件的性能。另一方面，采用常規(guī)鋁金屬化工藝時，當溫度達到400-450℃時，CMOS電路可靠性將受到嚴重的影響。從以上可以看出：如何克服后面高溫MEMS微結(jié)構(gòu)加工溫度對前面的已加工完的CMOS電路影響是解決單片集成MEMS系統(tǒng)關(guān)鍵所在。目前，國際上解決這個問題基本是通過3種方式：第一種是以難熔金屬化互連代替鋁金屬化互連，如，伯克利大學的以鎢代替鋁金屬互連方案，這樣提高容忍后續(xù)加工 大連水產(chǎn)學院本科畢業(yè)論文(設計) 外文翻譯 MEMS所需的高溫；第二種方式是通過尋找低制作溫度且機械性能優(yōu)良的材料代替多晶硅作為結(jié)構(gòu)層材料；第三種方式是利用CMOS本身已有結(jié)構(gòu)層作為MEMS結(jié)構(gòu)層。 pre-CMOS集成方法是先制造MEMS結(jié)構(gòu)后制造CMOS電路，這種集成CMOS技術(shù)雖然克服post-CMOS方法中MEMS高溫工藝對CMOS電路的影響，但由于存在垂直的微結(jié)構(gòu)，所以，存在傳感器與電路互連臺階覆蓋性問題，而且，在CMOS電路工藝過程中對微結(jié)構(gòu)的保護也是一個需要考慮的問題。甚至已優(yōu)化微調(diào)的CMOS工藝流程，例如：柵氧化可能被重摻雜的結(jié)構(gòu)層影響。另外，MEMS工藝過程中不能有任何的金屬或其他的材料，如壓電材料聚合物等，使得這種方法只適合一些特殊應用。 intermediate-CMOS是在CMOS電路生產(chǎn)過程中插入一些MEMS微細加工工藝來實現(xiàn)單片集成MEMS的方法。這種方法已很成熟，并已有很多商品化產(chǎn)品，也是研究最早一種單片集成方法，是解決pre-CMOS和post-CMOS方法存在問題有效方法，但是，由于需要對現(xiàn)有的標準CMOS或BiCMOS工藝進行較大的修改，因此，這種方法的使用有一定限制。 2.單片集成MEMS的主要技術(shù)現(xiàn)狀 目前，單片集成MEMS技術(shù)主要以post-CMOS技術(shù)為主，通過一系列的與CMOS工藝兼容的表面微細加工和體加工實現(xiàn)單片集成MEMS。又可分為2種：一種是在CMOS結(jié)構(gòu)層上面再淀積一層結(jié)構(gòu)層的微加工；另一種是直接以CMOS原有的結(jié)構(gòu)層作為MEMS結(jié)構(gòu)層的微加工。 2.1 淀積新的結(jié)構(gòu)材料作MEMS結(jié)構(gòu)的集成技術(shù) 2.1.1 多晶硅作為結(jié)構(gòu)層的集成表面微細加工技術(shù) 這種工藝典型代表是伯克利大學開發(fā)模塊集成CMOS與MEMS工藝（modular integration of CMOS with micro-structures，MICS），這種方法是以多晶硅為微結(jié)構(gòu)層，磷硅玻璃（PSG）作為犧牲層的表面微細加工技術(shù)。采用難熔金屬鎢的金屬化互連代替鋁金屬化互連以承受后面的生產(chǎn)多晶硅微結(jié)構(gòu)所需要的高溫，但是，在600℃時，鎢容易與硅形成反應，伯克利大學是通過在接觸孔上放一層TiN阻擋層來解決這一問題的。MICS工藝基本流程是：完成鎢金屬化的CMOS工藝后，淀積300×10-10nm低溫氧化物（LTO），然后，低壓化學氣相淀積200×10-10nm的氮化硅薄膜保護已生產(chǎn)的CMOS電路，腐蝕完微結(jié)構(gòu)與CMOS電路的接觸孔后，淀積第1層現(xiàn)場摻雜多晶硅（350×10-10）作為CMOS電路與微結(jié)構(gòu)的互連線，再在上面淀積1um厚的PSG作為犧牲層以及淀積厚度為2um多晶硅結(jié)構(gòu)層。通過在第2層多晶硅上再淀積一層0.5um的PSG，以及在氮氣環(huán)境下的1000℃快速退火1min來降低作為結(jié)構(gòu)層的多晶硅應力。最后，刻蝕多晶硅結(jié)構(gòu)圖形以及腐蝕掉其下面的犧牲層（PSG）以釋放微結(jié)構(gòu)。 2.1.2 以其他材料作結(jié)構(gòu)層集成表面微細加工技術(shù) 多晶硅鍺不僅有與多晶硅相似的優(yōu)良機械性能，而且，淀積溫度低與CMOS工藝兼容，所以，目前被廣泛研究。伯克利大學開發(fā)的基于硅鍺結(jié)構(gòu)層的工藝與MICS工藝基本相似。主要技術(shù)革新：第一，保護層采用不同的材料，以前MICS工藝采用835℃的LPCVD氮化硅，而現(xiàn)在則是采用兩層LTO和中間夾一層不定型硅（a-Si）作為CMOS電路保護層，其中，a-Si分兩步淀積，第一步淀積在450℃；第二步淀積則在410℃，這樣溫度是不會損壞鋁金屬化CMOS電路；第二，采用低淀積溫度多晶硅鍺作為結(jié)構(gòu)層材料，其低壓化學氣相淀積（LPCVD）溫度只有400℃，采用快速退火溫度也僅為550℃，時間為30s。而MICS工藝淀積多晶硅結(jié)構(gòu)溫度則超過600℃。從以上兩 點可知，由于整個后續(xù)MEMS加工溫度不超過450℃，所以，不會對鋁金屬化互連CMOS電路產(chǎn)生很大的影響。 采用鋁作為結(jié)構(gòu)層材料也會獲得很大成功，最為成功的是德州儀器開發(fā)低溫表面微細加工技術(shù)，并用這種技術(shù)成功生產(chǎn)了數(shù)字微鏡設備（DMD）。技術(shù)革新主要表現(xiàn)在采用濺射鋁作為結(jié)構(gòu)層材料，并且，采用光致抗蝕劑作為犧牲層，這種低溫后處理使得已生產(chǎn)的下面SRAM單元不被破壞 。 鋯鈦酸鉛（PZT）電材料因具有優(yōu)良的壓電性能、熱釋電性能、鐵電性能和介電性能而被廣泛應用在鐵電存儲器中以及作為高介質(zhì)材料。同時，還可以利用鋯鈦酸鉛壓電效應制作微傳感器以及微執(zhí)行器。PZT薄膜工藝與硅集成工藝兼容，如，目前的基于金屬有機化學氣相淀積（OCVD）方法制作PZT薄膜溫度已降低到430~75℃，這個溫度還在降低，因此，采用這種材料作為結(jié)構(gòu)層是很有希望與CMOS工藝集成的。 2.2 以原CMOS結(jié)構(gòu)層作MEMS結(jié)構(gòu)的集成技術(shù) 2.2.1 犧牲鋁的微加工技術(shù) 如果CMOS金屬化合物用作犧牲材料，則可能存在和CMOS工藝完全兼容的表面微細加工丁藝，這種方法被稱作犧牲鋁蝕刻（sacrificial aluminum etching，SALE）。在許多CMOS工藝過程中，都采用了兩層由鋁合金構(gòu)成的金屬層。第1層金屬作為犧牲層被清除，可以制造出電介質(zhì)金屬化合物；第2層由金屬和鈍化物組成，第2層金屬介于兩個電介質(zhì)之間，適當結(jié)構(gòu)化后，便可以作為反射鏡、電極、熱電阻或電熱調(diào)節(jié)器。其基本工藝過程包括：（1）保護電氣連接觸點不受到蝕刻；（2）腐蝕犧牲鋁層；（3）涮洗清除徼結(jié)構(gòu)里面的蝕刻劑；（4）烘干微機構(gòu)。 2.2.2 單晶體硅活化蝕刻和金屬化法 單體硅活化蝕刻和金屬化法（single crystal reactiveetching and metallization，SCREAM）可用于制造，梁、橋這樣的結(jié)構(gòu)，甚至可以用單晶硅制造更復雜的結(jié)構(gòu)。這種方法始于制造完的CMOS電路硅片，首先，淀積一層覆蓋接觸孔的氧化硅，這層氧化物保護CMOS電路免受后面工藝影響，并通過反應離子蝕刻（RIE）圖形化這層氧化物遮蔽層；然后，RIE蝕刻硅溝槽，深度可達到10um，氧化硅薄膜淀積下來，覆蓋在側(cè)面和水平面上。通過反應離子蝕刻掉水平面上的氧化物，而使豎直面受到保護，第二次反應離子蝕刻硅；最后，各向同性蝕刻硅，釋放出懸浮的微結(jié)構(gòu)，同時，蝕刻接觸孔氧化物，并濺射金屬，這層金屬化淀積物使大縱橫比的粱變成電容性元素，用厚的抗蝕劑作掩蔽模圖形化金屬層。由于SCREAM的每一步均在低于300℃的溫度下進行的，因此，是與CMOS電路兼容的。 2.2.3大縱橫比的CMOS-MEMS工藝 Gamegle Melloa大學開發(fā)的與CMOS兼容干法蝕刻方法，它應用各向同性硅蝕刻產(chǎn)生絕緣薄膜，CMOS介質(zhì)和金屬化層在這個工藝中不僅用作金屬互連，而且，還作為微機械結(jié)構(gòu)尾?；竟に囘^程為：首先，標準的CMOS工藝采用三層金屬0.5upmN阱工藝實現(xiàn)；其次，金屬層1和2被用作電活性層，而第3層作為微機械加工的蝕刻掩模。應用化合物CHF3／O2的反應離子蝕刻（RIE），使整個芯片上的鈍化層被清除掉，在第3層金屬斷開區(qū)域，CMOS薄膜夾層被一直蝕刻至基底，而上面覆蓋有第3層金屬的CMOS薄膜夾層則保留完好；最后，采用SP6／O2等離子在不蝕刻微結(jié)構(gòu)側(cè)壁情況下各向同性蝕刻硅襯底。狹窄的絕緣層和導電層融為一體制造出梁和橋，例如：梳狀驅(qū)動器這樣的微結(jié)構(gòu)。 2.2.4 體加工CMOS-MEMS工藝 主要是通過蝕刻硅襯底等體加工技術(shù)來形成所需的MEMS結(jié)構(gòu)，這種技術(shù)主要以蘇黎世大學為主?？梢詮恼嫖g刻硅襯底，也可以從反面蝕刻硅襯底，利用各向異性腐蝕（100）方向的特性，從硅的正面蝕刻是可以得到未封閉的微結(jié)構(gòu)，如，梁和支撐膜等，可選用的蝕刻劑可以是氫氧化四甲基銨水溶液（TMATH）或乙烯二胺溶液（EDP）。通過從已完成的硅片背部蝕該硅片可以得到封閉的介電薄膜，需要一個額外的掩模定義膜片的大小，通常采用的燭刻劑是KOH。 采用XeF2干法蝕刻的post-CMOS工藝也得到很大的發(fā)展。XeP2是一種各向異性硅蝕刻劑，蝕刻速度很高，它是惰性氣體氙的一種稀有化合物。XeP2既不蝕刻IC絕緣層，也不蝕刻鋁合金金屬化合物，因此，和CMOS完全兼容。經(jīng)過適當?shù)膮^(qū)域設計、連接和加掩模，在指定部位打開絕緣層，使基底硅局部暴露給蝕刻劑。因為XeF2即不蝕刻陶瓷，也不蝕刻塑料，從而適合集成CMOS微系統(tǒng)的微加工。使用這種方法可在已完成的CMOS芯片上無掩模蝕刻出微機構(gòu)。 3.發(fā)展趨勢 單片集成MEMS技術(shù)已開發(fā)10多年了，已得到了迅猛發(fā)展，也涌現(xiàn)出各種MEMS制造服務組織和企業(yè)，從而可以獲得一些組織或直接由特殊集成電路制造商提供MEMS加工。代表微系統(tǒng)IC技術(shù)發(fā)展方向的組織包括美國的MOSIS.Europractice和歐洲的TIMACMP；美國北卡羅納州的Croons集成微系統(tǒng)公司除了提供基本的CMOS工藝以外，還提供體微加工和表面徽加工、LIGA工藝以及多用戶微機電系統(tǒng)工藝等；美國桑迪亞國家實驗室開發(fā)的超平面多層多晶硅工藝也已商品化；在歐洲從事特殊應用集成電路制造技術(shù)研究的包括奧地利微系統(tǒng)公司和瑞士的EM微電子公司。還有很多基于傳感器的特殊硅工藝也已經(jīng)被研究出來，如，德國的羅伯特博施公司和挪威的SensoNor公司等。從目前來看，集成MEMS技術(shù)將有如下趨勢： （1）post-CMOS集成方法仍將是未來的主要開發(fā)技術(shù)，并將現(xiàn)有實驗室已開發(fā)的各種post-CMOS單片集成MEMS技術(shù)產(chǎn)業(yè)化； （2）在集成MEMS系統(tǒng)上集成更多的復雜的電路包括數(shù)字接口和微控制器，這樣得到功能更強大、價格便宜的智能系統(tǒng)； （3）開發(fā)封裝技術(shù)保護CMOS芯片免受環(huán)境的影響，不僅需要開發(fā)適應MEMS集成系統(tǒng)的封裝，而且，也需要開發(fā)能適應封裝的單片MEMS集成技術(shù)。 4.結(jié)束語 單片集成MEMS是實現(xiàn)智能傳感器的關(guān)鍵，也是IC業(yè)發(fā)展的一個重要方向。雖然目前各種方法都還存在一些問題，但是，隨著對其不斷的研究與CMOS工藝兼容性各種問題也會一一解決。本文對單片集成MEMS技術(shù)對工藝提出的要求進行了討論，并對目前各種單片集成MEMS技術(shù)特點、工藝流程進行了介紹，同時，還給出未來單片集成MEMS技術(shù)未來發(fā)展趨勢。 Monolithically integrated MEMS technology In the past 20 years, CMOS technology has become a major integrated circuit manufacturing technology, manufacturing costs decline at the same time, yield and production has also been greatly improved, COMS technology will continue to increase integration and reduce development of a special size. Today, CMOS integrated process not only be used in the design of integrated circuits, but also to be used in many micro-sensors and micro-actuator, so it can be integrated circuits and micro-sensor integrated with a powerful, intelligent sensors. With micro-sensor constantly expanding the scope of application of the sensor increasingly high demands of the future microsensor the main requirements are: miniaturization and integration of low-power and low-cost high-precision and long life; - and intelligent. Micromachined silicon integrated circuits and the integration of integration, to meet the above-mentioned requirements. At present, the majority of products integrated sensor using hybrid integrated, monolithic integration of a very small percentage. And the realization of single-chip integration is the key to achieving intelligent sensors, in particular monolithic integrated MEMS sensor technology is today's system-on-chip can achieve one of the key technologies. Clearly, monolithic integration of the various technical difficulties analysis of MEMS and have already given the various monolithic integration of MEMS technology is essential. 1. Monolithic integration of MEMS technology advantages and the challenges facing。 MEMS and CMOS achieve working together, the separate manufacturing CMOS MEMS sensors and integrated circuits, and then cut from their chips, fixed in a common substrate, and, bonded connection, thereby bringing the two integration, This is the so-called mixed (hybrid) method. This method does not produce MEMS manufacturing process for CMOS circuits pollution At the same time, both the production process Noninterference. However, due to signal bonding point and fuses, resulting in high-frequency applications, decline in the quality of signal transmission, and to develop two production lines to increase the cost of the product. In order to address some performance issues, and lower manufacturing costs, and proposed to do in the part of MEMS and CMOS circuits with a substrate, which is produced compatible with CMOS technology or monolithic integrated MEMS technology called CMOS-MEMS technology. This method relative hybrid method generally have the following advantages: First, the performance can be greatly improved, because parasitic capacitance and crosstalk phenomenon can be significantly reduced; second, hybrid method requires sophisticated technology to reduce packaging Sensor Interface affected, and monolithic integration requires packaging technology is relatively simple and therefore, lower cost sensors; third, monolithic integrated sensor array sensor technology is the need to overcome the array sensor and external decoding circuit an effective interconnect bottleneck; Fourth, the development of monolithic integrated mixed development of MEMS products than MEMS products for a short time, and to develop low cost. Monolithic integration of MEMS technology under some of MEMS devices and CMOS circuit can be divided into different order processing before CMOS (pre-CMOS), mixed CMOS (intermediate-CMOS), and after the CMOS (post-CMOS) integrated approach. Post-CMOS approach is in the processing of silicon CMOS circuits End, through some additional MEMS micro-processing technology to achieve monolithic integrated MEMS system, at present, monolithic integration of MEMS technology in this way mainly based. Post-CMOS approach is the main issue on MEMS processing temperature CMOS circuit performance in front of an impact on more serious is that the technology behind high-temperature MEMS processing temperature and metal CMOS process ahead of incompatibility. In the present study as the most polysilicon layer structure of the MEMS example, the densification of phosphorus glass annealing temperature is 950 ℃ due to a structural polysilicon layer of stress annealing temperature reached 1050 ℃, which will enable CMOS devices junction depth migration occurred. In particular 800 ℃ shallow junction devices junction depth migration will affect device performance. On the other hand, the conventional aluminum metallization process, when the temperature reaches 400-450 ℃, the reliability of CMOS circuits will be severely affected. From the above we can see that: how to overcome behind high-temperature MEMS processing temperature on the micro-structure of the front end processing has been the impact of CMOS circuits integrated MEMS single-chip solution is key to the system. At present, the international community is essential to resolve this issue through three ways: First is the interconnection of refractory metals instead of aluminum metal interconnect, for example, the University of Berkeley to replace tungsten aluminum metal interconnect programmes, such follow-up increased tolerance MEMS processing for high temperature; The second is produced by finding low temperature mechanical properties and excellent substitute materials as structural polysilicon layer; third way is to use its existing structure CMOS MEMS layer as a layer structure. Pre-CMOS integrated approach is to create structure MEMS manufacturing CMOS circuits, although this integrated CMOS technology to overcome post-CMOS method of high-temperature MEMS Technology on CMOS circuits affected, but because of the existence of micro-vertical structure, and therefore, there sensor and circuit interconnection level coverage, but also in the process of CMOS circuits on the micro-structure protection is also a need to consider the issue. Even fine-tune the optimization of CMOS process, such as: gate oxide may be heavily doped layer impact of the structure. In addition, the MEMS technology can not process any of the metal or other materials, such as piezoelectric polymers, and so on, makes this method only suitable for some special applications. Intermediate-CMOS circuits in the CMOS production process to insert some MEMS micro-processing technology to achieve monolithic integrated MEMS approach. This approach has been very mature and have a lot of commercialization of products, is the first study of a single-chip integration method is to solve the pre - and post-CMOS CMOS method effective method problems, but due to the need for the existing standard CMOS or larger BiCMOS process changes, therefore, the use of this method is limited. 2.The main monolithic integrated MEMS technology status At present, the monolithic integration of MEMS technology mainly to post-CMOS technologies, through a series of compatible with CMOS process on the surface micro-machining and processing to achieve monolithic integration of MEMS. Can be divided into two kinds: one is in the top layer CMOS structure to a structure layer deposition micro-machining; the other is directly CMOS layer structure as the original structure of the MEMS micro-machined. 2.1 Deposition of new structural materials for the structure of integrated MEMS technology 2.1.1 Polysilicon layer structure as the surface micro-machining technology integration This process is typical of modules developed at the University of Berkeley Integrated CMOS and MEMS Technology (modular integration of CMOS with micro-structures, MICS), this method is for the micro-structural polysilicon layer, phosphorus silicon glass (PSG) as a sacrificial layer The surface micro-machining technology. A refractory metal tungsten metal interconnect instead of aluminum metal interconnect to bear behind the polysilicon production needs of micro-structure of high-temperature, but at 600 ℃, tungsten and silicon form easily response by the University of Berkeley in the Contacts release a TiN barrier layer to address this problem. MICS process is the basic process: the completion of tungsten metal CMOS process, the deposition of 300 × 10-10nm low-temperature oxide (LTO), and then, low pressure chemical vapor deposition 200 × 10-10nm protection of the silicon nitride film has been produced CMOS circuits, micro-structure and corrosion End CMOS circuit contact hole, No. 1 layer deposition scene doped polysilicon (350 × 10-10), as CMOS circuits and micro-structure of interconnection lines, in the above deposition to a um PSG thick as a sacrificial layer thickness and deposition of 2 um polysilicon layer structure. No. 2 through another layer polysilicon deposition of a layer of 0.5 um PSG, as well as nitrogen environment in the 1000 ℃ rapid thermal annealing for 1 min as a structure to reduce stress polysilicon layer. Finally, the structure of graphics and polysilicon etching out its corrosion layer below the sacrifices (PSG) for the release of micro-structure. 2.1.2 Other materials for the structure of the surface micro-machining technology integration Polycrystalline silicon germanium polysilicon not only with the excellent mechanical properties similar, and, low temperature deposition compatible with the CMOS process, therefore, is being extensively studied. Developed at the University of Berkeley-based structural layer of silicon germanium technology and MICS technology similar. Major technological innovations: First, the protective layer using different materials, before 835 ℃ MICS process is the LPCVD silicon nitride, and now it is using a two-tier LTO and intermediate folder is not a stereotypical silicon (a-Si) as a CMOS circuit protective layer, in which the two-step deposition of a-Si, the first step in the deposition 450 ℃; step deposition in the 410 ℃, this will not damage the temperature of aluminum metal CMOS circuit; Second, the low amylin plot structure as a temperature polysilicon layer of germanium materials, the low pressure chemical vapor deposition (LPCVD) temperature only 400 ℃ using rapid thermal annealing temperature of only 5.5 ℃ for 30 s. MICS and the temperature polysilicon deposition of more than 600 ℃. From the above two points, we can see that the whole follow-up MEMS processing temperature does not exceed 450 ℃, therefore, not of aluminum metal interconnect CMOS circuits have greatly affected. Aluminum used as a structural material will be a great success, the most successful is the Texas Instruments developed cryogenic surface micro-machining technology, and use this technology successfully produced digital micromirror device (DMD). Technical innovation in the use of sputtering performance as aluminum structural material, and using photoresist as a sacrificial layer, which makes low-temperature post-processing production has been below the SRAM cells were not damaged. Lead zirconate titanate (PZT) of the material has an excellent result piezoelectric properties, pyroelectric properties of ferroelectric properties and dielectric properties and is widely used in ferroelectric memory, as well as high-dielectric materials. At the same time, we can also use lead zirconate titanate piezoelectric effect produced micro-sensors and micro-actuators. PZT thin film silicon technology and integration technology compatible, such as the present based on the metal-organic chemical vapor deposition (OCVD) Methods PZT thin films temperature has been reduced to 430 to 75 ℃, the temperature is lower, therefore, use of such materials as structural layer is a very hopeful and CMOS process integration. 2.2 CMOS structure to the original layer to the structure of integrated MEMS technology 2.2.1 Sacrifice aluminum micro-machining technology If CMOS metal compounds used for the expense of materials, there may be fully compatible with CMOS technology and surface micro-machining small art, this method is called sacrifice aluminum etching (sacrificial aluminum etching, SALE). In many CMOS process, use two layers of aluminum alloy by a metal layer. No. 1 as a sacrificial layer of metal was removed, can create metal dielectric compounds; Layer 2 and passivation of the metal component, 2-layer metal between two dielectric between appropriate structure, they could serve as a mirror electrodes, heat or electric resistance regulator. The basic process include: (1) the protection of electrical contacts are not connected etching (2) corrosion sacrifice aluminum layer; (3) removal rinsed Boundary structure inside the etching agent; (4)-drying bodies. 2.2.2 Monocrystal silicon etching and metal activation method. Monomer silicon etching and metal activation method (single crystal reactiveetching and metallization, SCREAM) can be used for manufacturing, beam, the bridge structure, and even silicon can be used to create more complex structures. This approach starts at the End manufacture silicon CMOS circuits, first of all, a layer of coverage deposition contact hole silicon oxide, oxide layer to protect it from the back of CMOS circuits affected, and through reactive ion etching (RIE) of this graphics Oxide layer shielding layer; then RIE etching silicon trench, the depth of up to 10 um, silicon oxide thin film deposition down, and the level of coverage in the side surface. By reactive ion etching of the oxide surface level off due to a vertical surface to be protected, the second reactive ion etching silicon; Finally, the isotropic etch silicon, the release of the microstructure of a suspension, at the same time, etching contact hole oxides, and Sputtering metal, this layer of metal deposition to the aspect ratio of the beam into a capacitive elements with thick resist masking agent for the graphics mode of metal layers. As each step of SCREAM are below 300 ℃ under the temperature and, therefore, is compatible with CMOS circuits. 2.2.3 Large aspect ratio of CMOS-MEMS Technology Gamegle Melloa University and the development of CMOS-compatible dry etching method, which isotropic silicon etch applications have insulation film, CMOS dielectric and metal layers in this process, not only for the metal interconnect, but also as a micro-mechanical stru